LDO circuit design without off-chip capacitors
SMIC 130nm process

The structure of the circuit includes a bandgap reference, a buffer, an LDO loop, and an over-temperature protection circuit

Specific indicators:
Band gap datum:
The output voltage is 1.2V
PSRR -61dB，
-40~125°C temperature drift 3mv

LDO
The loop gain is 72db and the bandwidth is 5M
The load regulation is 0.094
The input voltage is 3.3, and the output voltage is 1.8V
Psrr：-57db
The maximum current is 40mA

The circuit can be opened directly in the Cadence virtuoso, suitable for beginners, big guy do not disturb!

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